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Synapse Design Automation in Vietnam recruitment

Synapse Design is hiring Physical Design Engineers for the Vietnam Design Center. The Vietnam center is working on implementing digital ASICs from RTL to GDSII for networking, mobile and consumer applications in advance technology nodes at 28nm and 14nm. We are now seeking for:

- 1 to 4 years of PD Experience using Cadence or Synopsys tools.

Experience on block-level from RTL to GDSII
Experience in top-level floor-planning, partitioning, low power implementation required.

Engineers located in Vietnam will work directly with the US team with on-site opportunities in Europe, Asia and US.

If you are interesting, please send your resume at This e-mail address is being protected from spambots. You need JavaScript enabled to view it

Thanks

Below is the Job Description:

Job Description
The Physical Design (PD) Engineer will own the digital physical design and implementation of multiple blocks and/or chips from synthesis through manufacturing mask release for our advanced communication processors and chips. These Next Generation processors and chips are varying in size using a 28nm foundry process. The successful PD Engineer will run the full range of EDA software: synthesis, place and route, LEC, parasitic extraction, timing analysis and ECO, DRC, LVS, and others. The PD Engineer will succeed by participating in the maintenance and development of the physical design flows and methodologies. The PD Engineer will work closely with the RTL design, verification, CAD tools and the manufacturing test team. Employees are required following:
* Bachelors or Master's degree in Electrical-Electronic Engineering (or equivalent work experience)
* 1-4+ years' experience in physical design, automated place and route, static timing analysis and power grid design and analysis
* Understanding in VLSI, digital logic synthesis
* Interact with design team with purpose to solve problems and propose physical design engineering ideas
* Enforce RTL to GDSII (for chip or block designs) (synthesis, floor planning, placement, CTS, routing, STA)
* Understanding of Logical equivalency checking (LEC)
* Ability to do power analysis
* Exposure to physical verification (DRC, LVS, Antenna, DFM)
* Capability in Design for Manufacturing, Test (DFM, DFT) and Debug
* Develop and debug Timing constraint file (SDC)
* Analyze independently and plan all complex layout tasks related to design ECO technology limitations and project milestone requirements and deliver on time
* Linux scripting in C/C++, Perl, Awk or Tcl is desired
* Ability to write scripts to automate tasks and improve debug efficiency is desired
* Experience with Cadence, Synopsys, Mentor, Apache tool suite (DC, ICC, Primetime, PTPX, RTL Compiler, EDI, Calibre, RedHawk) is a plus

Non-experience engineers are welcome too, he/she will be trained on the job assignment