Trung tâm đào tạo thiết kế vi mạch Semicon

1. DFT Manager:
• The ideal candidate will have 5+ years of DFT experience, leading DFT efforts for SOC designs
• Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
• Experience developing DFT specifications and driving DFT architecture and methods for designs a plus
• Knowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools
• Knowledge of industry standards DFT and design tools
• Experience in debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG/1500 related issues a plus
• Experience with STA constraints development and analysis for DFT modes and SDF simulations a plus.

2. Senior DFT Engineer:
• The ideal candidate will have 2+ years of DFT experience, leading DFT efforts for SOC designs
• Knowledge about industrial standards and any/all of the following practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
• Knowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools
• Knowledge of industry standards DFT and design tools
• Possible Experience with STA constraints development and analysis for DFT modes and SDF simulations a plus.

3. Junior DFT Engineer:
• Completion of undergraduate program in Electrical Engineering or Computer Engineering.
• Strong analytical and critical thinking skills.
• Good communication skills, positive attitude, and ability to work in a team environment.
• Exposure to a scripting languages such as TCL, Perl, and/or Make is a plus.
• Good understanding of Fundamentals of Synchronous logic design.
• Coursework in digital IC design a plus.
• Experience with Verilog coding and DFT implementation a plus.
• Project or industry experience in ASIC is a plus.