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ASIC Design Engineer Intern (Multiple Openings)

ASIC Design Engineer Intern (Multiple Openings)

 

   Uniquify

2030 Fortune Drive — Suite 200 - San Jose, CA 95131.

Hạn Chót Nộp Hồ Sơ: 30-09-2013

Cấp Bậc
Mới tốt nghiệp/Thực tập sinh

Headquartered in Silicon Valley, Uniquify (www.uniquify.com) is a privately held ASIC design services and semiconductor IP solutions provider. The company has design centers in Santa Clara, California and Pune, India; and it maintains sales offices in Austin, Santa Clara, Seoul, Taipei and Tel Aviv. Uniquify provides leading edge SoC design and IP solutions. We offer a wide range of “ideas2silicon” services that span design specification, RTL, logic design/verification, physical implementation, and manufacturing operations. Perseus, our proprietary design management system allows us to deliver consistent design closure and reduced schedules on even the most complex SoC designs. We are now setting up Uniquify in Viet Nam and seeking for candidates working in Viet Nam.

Qui mô công ty: 25-99

Nơi Làm Viêc
Hồ Chí Minh
Ngành Nghề
Điện/Điện tử
Công nghệ cao
IT-Phần cứng/Mạng

Ngôn Ngữ Trình Bày Hồ Sơ
Tiếng Anh
 

Mô Tả Công Việc

• A sharp and highly motivated person whom our experienced ASIC design team can teach and train into an excellent ASIC design engineer. 
• Work closely with our industry experienced physical design and/or logical design ASIC team developing multi-million gate state of the art System-on-Chip (SoC) designs. 
• Gain understanding and practical knowledge in physical design of ASICs. 
• The internship will focus on the following but not limited to synthesis, simulation and verification, static timing analysis, power analysis, as well as physical implementation (ex. floorplanning, place&route) and verification.
 

Yêu Cầu Công Việc

• In the last year of undergraduate program in Electrical Engineering or Computer Engineering.
• Strong analytical and critical thinking skills.
• Good communication skills, positive attitude, and ability to work in a team environment.
• Exposure to a scripting languages such as TCL, Perl, and/or Make is a plus.
• Good understanding of Fundamentals of Synchronous logic design.
• Coursework in digital IC design a plus.
• Experience with Verilog coding and verification a plus.
• Project or industry experience in ASIC is a plus.]
 
 Theo vietnamwork

 

 
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