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Please refer to dual port RAM. Please see code of this in this article.

Table 1. General Benefits / Drawbacks of Single Port
Asynchronous Synchronous
Benefits 

More simple interface
Legacy design that is common
Higher bandwidth capabilities
Drawbacks Lower bandwidth capabilities More complicated interface

Also, processors that are fast don't necessarily mean their external memory interfaces are fast. Some 400-MHz DSPs offer asynchronous SRAM interfaces only. In general, it is best to try to match the maximum speed and type of interfaces that the processors offer. For example, if both processors offer synchronous memory interfaces, one can run at a maximum of 70 MHz, one can run at a maximum of 133 MHz, then a synchronous dual-port that runs at least 133 MHz would be recommended.

1 //-----------------------------------------------------
2 // Design Name : ram_sp_sr_sw
3 // File Name : ram_sp_sr_sw.v
4 // Function : Synchronous read write RAM 
5 // Coder : -
6 //-----------------------------------------------------
7 module ram_sp_sr_sw (
8 clk , // Clock Input
9 address , // Address Input
10 data , // Data bi-directional
11 cs , // Chip Select
12 we , // Write Enable/Read Enable
13 oe // Output Enable
14 ); 
15 
16 parameter DATA_WIDTH = 8 ;
17 parameter ADDR_WIDTH = 8 ;
18 parameter RAM_DEPTH = 1 << ADDR_WIDTH;
19 
20 //--------------Input Ports----------------------- 
21 input clk ;
22 input [ADDR_WIDTH-1:0] address ;
23 input cs ;
24 input we ;
25 input oe ; 
26 
27 //--------------Inout Ports----------------------- 
28 inout [DATA_WIDTH-1:0] data ;
29 
30 //--------------Internal variables---------------- 
31 reg [DATA_WIDTH-1:0] data_out ;
32 reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
33 reg oe_r;
34 
35 //--------------Code Starts Here------------------ 
36 
37 // Tri-State Buffer control 
38 // output : When we = 0, oe = 1, cs = 1
39 assign data = (cs && oe && ! we) ? data_out : 8'bz; 
40 
41 // Memory Write Block 
42 // Write Operation : When we = 1, cs = 1
43 always @ (posedge clk)
44 begin : MEM_WRITE
45 if ( cs && we ) begin
46 mem[address] = data;
47 end
48 end
49 
50 // Memory Read Block 
51 // Read Operation : When we = 0, oe = 1, cs = 1
52 always @ (posedge clk)
53 begin : MEM_READ
54 if (cs && ! we && oe) begin
55 data_out = mem[address];
56 oe_r = 1;
57 end else begin
58 oe_r = 0;
59 end
60 end
61 
62 endmodule // End of Module ram_sp_sr_sw