AAL

Asynchronous Transfer Mode Adaption Layer

ABIST

Automatic Built-In Self-Test

ACPI

Advanced Configuration and Power Interface

ACPR

Adjacent-channel power ratio

ADC

Analog to Digital Converter

AES

Advanced Encryption Standard.

AMBA

Advanced Microcontroller Bus Architecture

AMHS

Automated material handling system .

AQL

Acceptable Quality Level

ARC

Antireflective coating.

ASCII

American Standard Code for Information Interchange

ASIC

Application Specific Integrated Circuit

ATE

Automatic Test Equipment.

ATPG

Automatic Test Pattern Generation

AWG

Arbitrary waveform generator

BCD

Binary Coded Decimal

BERT

Bit Error Rate Tester

BGA

Ball grid Array

BIST

Built In Self Test

BIT

Binary Digit

BJT

Bipolar Junction Transistors

BOC

Board-On-Chip

BPSK

Binary Phase Shift Keying

CAD

Computer Aided Design

CAN

Controller Area Network

CDMA

Code Division Multiple Access

CISC

Complex instruction set computer

CMOS

Complementary Metal Oxide Semiconductor

CMP

Chemical-Mechanical Planarization

CPLD

Complex Programmable Logic Device

CRON

Command Run ON

CRT

Constrained Random Testing

CVD

Chemical Vapor Deposition

DAC

Digital to Analog Converter

DEF

Design Exchange Format

DES

Data Encryption Standards

DFT

Design For Test

DIP

Dual In line Package

DLP

Digital light Processing

DPD

Deep Power Down

DRAM

Dynamic Random Access Memory

DRC

Design Rule Check

DRIE

Deep reactive Ion Etching

DS

Selectable Drive Strength

DSM

Deep Sub-Micron.

DSP

Digital Signal Processor

DTL

Diode Transistor Logic

DUT

Device Under Test

DXF

The autodesk Drawing exchange

EB

Exabyte – 2^60 bytes or 1024 petabytes.

EB

Electronic Book

ECAD

Electronic Computer-Aided Design

ECL

Emitter Coupled Logic

ECO

Engineering Change Order

ECU

Electronic Control Unit

EDA

Electronic Design Automation.

EDC

Error Detection Code

EDI

Electronic Data Interchange

EDIF

Electronic Design Interchange Format

EDP

Electronic Data Processing

EEPROM

Electrically Erasable Programmable Read-Only Memory

EMC

Electromagnetic Compatibility

EMMS

Electronic Mail and Message System

EMS

Expanded memory specification.

EPLD

Erasable programmable logic device.

EPROM

Erasable Programmable Read-Only Memory

ESP

Electronic Stability Program

Fab

Fabrication facility

FBGA

Fine-pitch Ball Grid Array

FED

Field emission Display

FEOL

Front end-of-line.

FET

Field Effect Transistors

FF

Flip-Flop

FIFO

First In First Out

FIR

Finite Impulse Response

FLI

Foreign Language Interface – related to VHDL

FMEA

Failure Mode And Effects Analysis

FPGA

Field Programmable Gate Array

FSM

Finite State Machine

FTY

Final Test Yield.

GDSII

Graphic Data System II

GPRS

General Packet Radio Service

GPS

Global Positioning System

GSM

Global System for Mobile Communications

GUI

Graphical User Interface

HAL

Hardware Abstraction Layer

HDLs

Hardware Description Languages

HEMT

High Electron Mobility Transistor

IC

Integrated Circuits

IEEE

The Institute of Electrical and Electronics Engineers

IGBT

Insulated Gate Bipolar Transistor

IIR

Infinite Impulse Response

IMPATT Diode

Impact Ionization Avalanche Transit-Time

IR

Infrared

ITRS

International Technology Roadmap for Semiconductors

JTAG

Joint Test Action Group

KB

Kilobyte – 1024 bytes or 2^10 bytes.

Kbps

Kilobits Per Second

LED

Light Emitting Diode

LEF

Library Exchange Format

LEF

Layout Exchange Format

LFSR

Linear Feedback Shift Register

LIN

Local Interconnect Network

LSB

Least Significant Bit

LSI

Large Scale Integration

MAE

Metropolitan Area Exchange

MAN

Metropolitan Area Network

MAP

Manifold Absolut Pressure

MCM

Multi Chip Module

MEMS

Micro-Electro-Mechanical Systems

MESFET

Metal-Semiconductor Field-Effect Transistor

MIPI

The Mobile Industry Processor Interface

MIPS

Microprocessor without Interlocked Pipeline Stages

MISC

Minimal instruction set computer

MMIC

Microwave monolithic Integrated Circuit

MODFET

Modulation Doped Field Effect Transistor

MOEMS

Micro Opto Electro Mechanical Systems

MOS

Metal Oxide Semiconductor

MPSoC

Multi-Processor System-On-Chip

MSB

Most significant Bit

MSI

Medium Scale Integration

MST

Micro-System-Technology

MUMPs

Multi-User MEMS Processes

NEMS

Nanoelectromechanical systems

NMOS

nType Metal Oxide Semiconductors.

OCTS

On-Chip Temperature Sensor

OEIC

Optoelectronic Integrated Circuit.

OISC

One instruction set computer

OLED

Organic Light Emitting Diode

OTA

Operational Transconductance Amplifier

OVI

Open Verilog International

OVL

Open Verification Library

OVM

Open Verification Methodology

PAL

Programmable array logic.

PASR

Partial Array Self-Refresh

PB

Petabyte – 2^50 bytes.

PBET

Performance-based equipment training.

PCB

Printed Circuit Board.

PDC

Passive Data Collection

PDEF

Physical Design Exchange Format

PDLY

Photo Defect Limited Yield.

PECVD

Plasma-enhanced chemical vapor deposition.

PERL

Practical Extraction and Report Language

PIC

Photonic Integrated Circuit.

PIC

Photonic Integrated Circuit.

PIN

Pin Identification Number

PLC

Planar Light-wave Circuit.

PLD

Programmable Logic Devices

PLI

Programming Language Interface

PMOS

pType Metal Oxide Semiconductor.

PSK

Phase Shift Keying

PWP

Particles per Wafer Pass

QPSK

Quadrature Phase Shift Keying

RAL

Registry Access Library

RAM

Random Access Memory

RFID

Radio Frequency Identification

RISC

Reduced Instruction Set Computer

ROM

Read Only Memory

RTL

Register Transfer Level

SAIF

Switching Activity Interchange Format

SCR

Silicon Controlled Rectifier

SDF

Standard Delay Format

SDRAM

Synchronous Dynamic Random Access Memory

SIP

Single In line Package

SOA

Semiconductor Optical Amplifier.

SOC

System On Chip

SOI

Silicon On Insulator.

SPEF

Standard Parasitics Exchange Format

SPICE

Simulation Program for Integrated Circuits Emphasis

SSI

Small Scale Integration

STCI

Serial Test and configuration Interface

SV

System Verilog

TA

Ambient temperature

TCSR

Temperature-Compensated Self-Refresh

TLF

Timing Library Format

TTL

Transistor-Transistor Logic

TUNNET

Tunnel Injection Transit-Time diode

ULSI

Ultra Large Scale Integration

UPF

Unified Power Format

URISC

Ultimate RISC

USB

Universal Serial Bus

VCD

Value Change Dump

VCD

Virtual Circuit Descriptor.

VDSL

Very High Data Digital Subscriber Line.

VHDL

Very high speed integrated circuit Hardware Description Language

VIS

Verification Interacting with Synthesis

VITAL

VHDL Initiative Toward ASIC Libraries

VLIW

Very Long Instruction Word

VLSI

Very Large Scale Integration

WAIS

Wide Area Information Service

WAN

Wide Area Network

WAP

Wireless Application Protocol

WSI

Wafer Scale Integration

XOR

Exclusive OR

YB

Yottabyte – 2^80 bytes, or 1024 zettabytes

Yield

The yield is the percentage of defect-free (usable) die on a silicon wafer.

ZB

Zettabyte – 2^70 bytes, or 1024 exabytes.

ZISC

Zero Instruction Set Computer